Integrated circuits (IC) manufacturers are employing finer circuit widths, low dielectric constant (low-k) materials, and other technologies to make small, high-speed semiconductor devices. Along with these advancements, the challenges of maintaining yield and throughput have also increased. With regard to reliability, the presence of low-k materials near die corners increases the chances of crack formations, especially in the sawing process.
A semiconductor wafer typically comprises isolated dies (or chips) separated from each other by scribe lines. Individual dies within the wafer contain circuitry, and the dies are separated by sawing. A typical problem is that the low-k dielectric materials in dies are prone to damage incurred by stress introduced by the sawing process. When cracks form in low-k dielectric materials, copper lines in the low-k dielectric materials may be damaged.
Conventionally, dies may be inspected after the sawing process using an optical microscope (OM). However, OM inspection is objective, and hence is unreliable. Particularly, it is difficult to differentiate whether the damage is a backside chipping of the semiconductor die or an inter-metal dielectric (IMD) crack. The backside chipping can be easily solved by adjusting the sawing process, while the cracking of low-k dielectric materials is a much harder issue to solve. Without being able to reliably identify the root cause of the problem, it is hard to determine the action to be taken. What is needed, therefore, is a mean for reliably determining the quality of dies after sawing processes.